The present invention relates to a method for planning a layout for an LSI pattern with optical proximity corrections ensured, a method for generating mask data and a method for forming an LSI pattern using these methods.
Recently, as a semiconductor large-scale integrated circuit (LSI) device has been downsized, a photolithographic step, which is one of the main process steps of an LSI fabrication process, has been affected by optical proximity effects more and more seriously. Specifically, a deviation of a feature size of a pattern actually transferred onto a resist from that of a mask pattern formed on a reticle has almost reached a non-negligible level. That is to say, if the feature size of an originally designed pattern is automatically applied to the mask pattern, then the size of the actually transferred pattern is likely to deviate from the originally designed one. This problem is particularly noticeable in a transistor, which plays a key role in determining the operability of an LSI. In this specification, a feature size of a pattern originally designed will be called a xe2x80x9cdesigned sizexe2x80x9d, that of a pattern formed on a reticle or mask a xe2x80x9cmask sizexe2x80x9d and that of a pattern actually transferred onto a resist an xe2x80x9cactual sizexe2x80x9d, respectively.
Furthermore, every time an LSI of a new generation alternates with one of an older generation, the feature size of the LSI should be reduced discontinuously. For example, process technology of 0.18, xcexcm generation has lately alternated with that of 0.25 xcexcm generation. In this manner, a transistor feature size like the gate length thereof is usually reduced by about 70%. Whenever the gate length is reduced in this manner, one expects that the area of a cell implementing a circuit with the same function can also be reduced by about 50%, which is the square of 70%. This shrinkage rate is achievable by introducing a state-of-the-art exposure system using a radiation source with an even shorter wavelength or by improving the lithographic process itself.
These days, however, it has become more and more difficult to attain this shrinkage rate just by introducing a new system or improving the process. This is because the increase in deviation of an actual size from a mask size often prevents design rules, which are defined to ensure proper circuit operation, from achieving the 70% shrinkage rate. Examples of the design rules include the size of an extension of a gate and a contact margin.
FIG. 20(a) illustrates an originally designed pattern 100A and an actually transferred pattern 100B of an ordinary field effect transistor (FET). As shown in FIG. 20(a), the designed pattern 100A includes a gate pattern 101 to be shaped into a gate layer and an active layer pattern 102 to be shaped into an active layer. In the actually transferred pattern 10B, the width of the gate pattern 111 is smaller than its originally designed size, and both edge portions 111a of the gate pattern 111 no longer exist. If the portions of the gate pattern 111 overlapping with the active layer pattern 112 have been partially lost this way, then the transistor cannot operate normally.
To solve such a problem, extensions 101a are provided for both edges of the gate pattern 101 so as to extend from the active layer pattern 102 in the gate width direction as shown in FIG. 20(b). As the size of a line pattern, which is called a xe2x80x9cgate length 101bxe2x80x9d decreases, the areas of the edge portions of the gate pattern 101 to be lost increase. In other words, the size 101c of the extensions 101a does not decrease proportionally to the gate length 101b. Accordingly, when the gate length 101b is to be reduced, the size 101c of the extensions 101a of the gate pattern 101 should be increased to ensure proper operation for the transistor. Thus, it has become more and more difficult for the design rule concerning the extension size 101c to achieve the 70% shrinkage rate.
In spite of the circumstances such as these, the design rule is still defined based on the deviation of an actual size from a mask size. For example, the design rule is defined by the 70% shrinkage rate compared to the previous generation. Thus, to reduce the total area of the circuit patterns, the design rule defined based on the 70% shrinkage rate is prioritized and applied to even a pattern that cannot satisfy the design rule completely, e.g., the extension size 101c of the gate pattern 101.
Thereafter, a cell library is made up of a plurality of circuit patterns that have been designed in accordance with the design rule. LSI chip data is generated using the cell library to determine final conditions for the fabrication process. Based on these final process conditions, the deviation of an actual size from a mask size, which has been caused due to proximity effects, is estimated, thereby generating data for a mask layout that has been modified to eliminate the deviation of the actual size from the designed one. In this case, the actual sizes are estimated relative to the mask sizes using empirical models that reflect various conditions for estimating the actual sizes under predefined process conditions.
For example, in a portion of a circuit pattern where an actual size is thinner than its mask size, the mask size is thickened compared to the originally designed one. Conversely, in a portion of a circuit pattern where an actual size is thicker than its mask size, the mask size is thinned compared to the originally designed one. A mask pattern that is formed in view of optical proximity effects in this manner is called an xe2x80x9coptical proximity corrected (OPC)xe2x80x9d pattern.
According to the prior art method for generating LSI mask data, however, it is not until all the circuit patterns have been defined (i.e., while mask pattern data is being generated) that the OPC patterns are made. Thus, the OPC patterns could not be formed in some cases.
For example, consider a case shown in FIG. 20(a) where the edges of the gate pattern 101 disappear. In such a situation, even if the mask size for the extensions 101a of the gate pattern 101 should be corrected to match its actual size with the size originally designed for the circuit pattern, the size 101c of the extensions 101a could not be changed. For instance, this size change is impermissible if the space between the extensions 101a and surrounding patterns thereof is of the required minimum size defined by the resolution limit.
Furthermore, the prior art method for generating mask data has various drawbacks including the following:
(1) A design rule defined without taking proximity effect corrections into account would result in an excessively increased mask size.
The proximity effects on the gate pattern can be compensated for by various techniques other than the extension of the extensions. For example, where gates are laid out with relatively wide space interposed therebetween, a hammerhead pattern may be added to each extension of a gate pattern that is not located over the active layer of a transistor. This hammerhead pattern does not extend the extension in the gate width direction, but expands only the edges of the extension in the gate longitudinal direction, thereby preventing the actual size of the gate pattern from shrinking too much at its edges in the gate width direction. In this manner, the proximity effect corrections can be made not only by compensating for the deviation of the actual size from the mask size but also by minimizing the deviation. Accordingly, if the size deviation was simply expected and a design rule was defined based on the result without estimating how much the deviation can be reduced by forming an OPC pattern, then the mask size determined would be unnecessarily large.
(2) In general, circuit patterns are made in accordance with a basic pattern placement rule and process conditions are defined to minimize a variation in sizes of patterns actually formed and a deviation of each actual size from its mask size. However, another pattern placement rule, which is different from that applied to the definition of the process conditions, is applied to OPC patterns. Thus, the process conditions defined are not always best suited to the placement rule for the OPC patterns.
Suppose circuit patterns have been defined with a pattern-to-pattern space minimized but the actual size of the space is larger than the originally designed one. In such a case, to make the size of the space between OPC patterns smaller than that once defined for the circuit patterns, the minimum space between the OPC patterns should be reduced from the minimum pattern-to-pattern space that was defined when the process conditions were determined. Accordingly, if the process conditions did not change at all, then the size of a pattern actually formed using the OPC pattern should almost match the size originally designed for the circuit pattern. Actually, though, the process conditions are variable during the fabrication process, thus making the actual size non-uniform due to the variation. This is because if an actual size is reduced, then optimum process conditions usually change to minimize the size non-uniformity due to the variation of process conditions. In an extreme case, even a basic exposure method such as super-resolution exposure or phase shift masking should be changed to suppress the size non-uniformity.
(3) Although final process conditions for an LSI are determined just before the actual fabrication thereof, details of OPC patterns cannot be defined until specific process conditions are determined.
In developing an LSI, design of circuit patterns to be registered at a cell library is started as early as more than 6 months before the fabrication of the LSI. However, since the process conditions are determined just before the fabrication, details of OPC patterns cannot be defined at an early stage. Accordingly, it is difficult to design circuit patterns for a cell library in view of final OPC patterns to solve the problem (1).
(4) An OPC pattern is made based on only a deviation of an actual size obtained under predetermined process conditions from a size originally designed for a circuit pattern. A design rule, which is ordinarily defined such that a feature size of the previous generation should be reduced by 70%, is applied to the circuit pattern. Although the 70% shrinkage may be effectively applicable to some LSI""s, other LSI""s may require a different shrinkage rate.
For example, in making an LSI with the same function and the same chip area based on a new design rule, that LSI might be obtained at a shrinkage rate of 50%. Furthermore, in an actual circuit pattern, the actual size does not have to exactly match the originally designed one in every part of the circuit. That is to say, some parts of a circuit may require an exact match between the actual and designed sizes to ensure proper operation for the circuit, but other parts thereof may allow some size deviation. Accordingly, if a circuit is designed such that all the actual sizes thereof are reduced by 70% compared to the older generation, then unnecessarily stringent conditions will be imposed on the LSI fabrication, thus making it much harder to obtain a desired LSI.
An object of the present invention is performing optical proximity corrections effectively in such a manner as to downsize an LSI just as intended and to form circuit patterns that will make the LSI fully operative.
To achieve this object, according to an inventive method for planning a layout for an LSI pattern or generating mask data for an LSI, optical proximity corrected patterns are formed as mask data for circuit patterns being designed. Also, a design rule is defined to make the corrected patterns effectively applicable while the circuit patterns are being designed.
Specifically, an inventive method for planning a layout for an LSI pattern includes the steps of: designing circuit patterns included in the LSI pattern; making an initial placement for the circuit patterns designed; performing optical proximity corrections on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns; and evaluating effectiveness of the proximity corrections. If the effectiveness of the corrections is negated, the method further includes the steps of: changing a design rule defining the circuit patterns to make the corrections effective; and making a re-placement for the initially placed circuit patterns in accordance with the design rule changed.
According to the inventive method for planning an LSI pattern layout, optical proximity corrected patterns are generated first, and then a design rule defining circuit patterns is changed to make the corrections effective. Thus, the present invention eliminates a situation, where optical proximity corrections are no longer applicable to a mask pattern formed by transferring a designed pattern, as is often the case with the prior art.
In one embodiment of the present invention, the step of forming the corrected patterns preferably includes the step of setting specifications of the corrected patterns to be made. The step of evaluating preferably includes the step of changing the specifications to make the corrections effective if the effectiveness of the corrections is negated.
In another embodiment of the present invention, the step of making the re-placement preferably includes the step of forming multiple re-placement patterns and selecting one of the re-placement patterns that minimizes a total circuit area.
In still another embodiment, the method may further include the step of defining the design rule such that the circuit patterns can be laid out to make the corrections effective. The step of making the initial placement or the step of making the re-placement may include the step of placing the circuit patterns in accordance with the design rule.
In this case, the step of defining the design rule preferably includes the step of defining multiple design rules and selecting one of the design rules that minimizes a total circuit area.
In an alternate embodiment, the method may further include the steps of: setting specifications of the corrected patterns to be made; defining a rule of placing the corrected patterns such that the proximity corrections can be performed effectively using the corrected patterns; and forming the corrected patterns according to the specifications of the corrected patterns to be made and on the rule of placing the corrected patterns, thereby defining the design rule.
In this case, the method may further include the steps of: evaluating effectiveness of the proximity corrections for the circuit patterns that have been placed in accordance with the design rule; and modifying the specifications of the corrected patterns to be made or the rule of placing the corrected patterns to make the corrections effective if the effectiveness of the corrections is negated.
In still another embodiment, the step of evaluating may include the step of determining whether or not an expected actual size falls within a predetermined range by performing a process simulation including at least one of lithography and etching process steps.
In this case, the lithography process step in the process simulation preferably includes determining whether or not the expected actual size falls within the predetermined range even if an exposure dose or focus has changed so much as to exceed a process margin range.
Alternatively, it may be determined in the process simulation whether or not an expected size of a transistor in a gate longitudinal direction falls within the predetermined range.
As another alternative, it may also be determined in the process simulation whether or not an expected length of a portion of a transistor gate extending from an active layer in a gate width direction falls within the predetermined range.
A first inventive LSI pattern forming method includes the steps of: a) designing circuit patterns included in the LSI pattern; b) making an initial placement for the circuit patterns designed; c) performing optical proximity corrections on at least two of the circuit patterns that have been initially placed to be adjacent to or cross each other, thereby forming optical proximity corrected patterns out of the adjacent or crossing circuit patterns; and d) evaluating effectiveness of the proximity corrections under predetermined process conditions. If the effectiveness of the corrections is negated, then the method further includes the steps of: e) changing a design rule defining the circuit patterns to make the corrections effective; f) making a replacement for the initially placed circuit patterns in accordance with the design rule changed; g) producing a mask using the corrected patterns; and h) defining the circuit patterns on a semiconductor substrate under the predetermined process conditions by using the mask produced.
According to the first inventive LSI pattern forming method, circuit patterns (i.e., actually transferred patterns) are formed on a resist film, for example, using a mask that has been produced by the inventive LSI pattern layout planning method. Thus, these circuit patterns ensure proper operation for the resultant circuit.
In one embodiment of the present invention, the first LSI pattern forming method may further include the step of estimating process yield expectedly attainable when the produced mask is used under the predetermined process conditions after the step g) has been performed. And if the estimate is short of a target value, the method may further include the step of modifying the predetermined process conditions to make the estimate reach the target value and repeatedly performing the steps a) through g).
A first inventive LSI mask data generating method includes the step of a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns. Each said corrected pattern of the first group will not be changed in shape even when process conditions are modified, while each said corrected pattern of the second group will be changed in shape if the process conditions are modified. The method further includes the steps of: b) generating cell-level optical proximity corrected pattern data from the first group of corrected patterns when the circuit patterns are designed; and c) generating chip-level optical proximity corrected pattern data from the second group of corrected patterns when chip data is generated from the circuit patterns.
According to the first inventive LSI mask data generating method, even if optical proximity corrections are made in advance on the first group of corrected patterns, those patterns of the first group can be registered at a library. Also, since the first group of corrected patterns greatly affects cell areas, the corrected patterns are determined at a cell level, i.e., while the cells are being designed. Accordingly, the areas of the cells to be produced finally based on the corrected patterns can be estimated accurately. Furthermore, since the optical proximity corrections can be made on a cell-by-cell basis, the specifications of optical proximity corrected patterns to be made can be determined for each cell or block.
In one embodiment of the present invention, the step b) may include the step of evaluating effectiveness of optical proximity corrections represented by the cell-level corrected pattern data generated. If the effectiveness of the corrections is negated, the method may further include the step of modifying the cell-level corrected pattern data or circuit patterns corresponding to the cell-level corrected pattern data to make the corrections effective and then re-evaluating effectiveness of the corrections. And if the effectiveness of the corrections is affirmed, the method may include the step of registering the cell-level corrected pattern data at a cell library.
A second inventive LSI mask data generating method includes the step of a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns. Each said corrected pattern of the first group will not be changed in shape even when process conditions are modified, while each said corrected pattern of the second group will be changed in shape if the process conditions are modified. The method further includes the steps of: b) setting specifications of cell-level optical proximity corrected patterns to be made for the first group of corrected patterns; c) designing the circuit patterns; and d) evaluating effectiveness of optical proximity corrections if the cell-level corrected patterns, which have been made for the first group of corrected patterns to the specifications of the cell-level corrected patterns, are used. If the effectiveness of the corrections is negated, the method further includes the step of e) modifying ineffective circuit patterns to make the corrections effective and re-evaluating effectiveness of the corrections. And if the effectiveness of the corrections is affirmed, the method further includes the steps of: f) registering the circuit patterns, belonging to the first and second groups of corrected patterns, at a cell library; g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library; h) setting specifications of chip-level optical proximity corrected patterns to be made for the second group of corrected patterns; i) generating cell-level optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the cell-level corrected patterns; and j) generating chip-level optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the chip-level corrected patterns.
According to the second inventive LSI mask data generating method, specifications of cell-level corrected patterns are set for the circuit patterns belonging to the first group of corrected patterns, and those circuit patterns are registered at a cell library. Thereafter, when mask data is generated, cell- and chip-level corrected patterns with a huge data volume are made using the cell library. Accordingly, that huge volume of data can be managed more easily.
A third inventive LSI mask data generating method includes the step of a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns. Each said corrected pattern of the first group will not be changed in shape even when process conditions are modified, while each said corrected pattern of the second group will be changed in shape if the process conditions are modified. The method further includes the steps of: b) setting specifications of cell-level optical proximity corrected patterns to be made for the first group of corrected patterns; c) designing the circuit patterns; and d) evaluating effectiveness of optical proximity corrections if the cell-level corrected patterns, which have been made for the first group of corrected patterns to the specifications of the cell-level corrected patterns, are used. If the effectiveness of the corrections is negated, the method includes the step of e) modifying ineffective circuit patterns or the specifications of the cell-level corrected patterns corresponding to the circuit patterns to make the corrections effective and re-evaluating effectiveness of the corrections. And if the effectiveness of the corrections is affirmed, the method further includes the steps of: f) registering not only the circuit patterns belonging to the first group of corrected patterns and the specifications of the cell-level corrected patterns corresponding to the circuit patterns, but also the circuit patterns belonging to the second group of corrected patterns at a cell library; g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library; h) generating cell-level optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the cell-level corrected patterns; and i) generating chip-level optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the chip-level corrected patterns.
In one embodiment of the first through third inventive LSI mask data generating methods, if the corrections are effectively applicable to multiple layouts for circuit patterns, the step of evaluating preferably includes the step of selecting one of the layouts that results in a circuit area equal to or smaller than a predetermined value.
In this particular embodiment, the cell-level corrected pattern data preferably includes serif patterns, hammerhead patterns or in-section patterns.
A fourth inventive LSI mask data generating method includes the step of a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns. Each said corrected pattern of the first group is defined by circuit patterns placed to cover multiple layers, while each said corrected pattern of the second group is defined by circuit patterns placed within a single layer. The method further includes the steps of: b) generating interlayer optical proximity corrected pattern data from the first group of corrected patterns in designing the circuit patterns; and c) generating intralayer optical proximity corrected pattern data from the second group of corrected patterns in generating chip data from the circuit patterns.
According to the fourth inventive LSI mask data generating method, even if optical proximity corrections are made in advance on the first group of corrected patterns, those patterns of the first group can be registered at a library. Also, since the first group of corrected patterns greatly affects cell areas, the corrected patterns are determined at a cell level, i.e., while the cells are being designed. Accordingly, the areas of the cells to be produced finally based on the corrected patterns can be estimated accurately. Furthermore, since the optical proximity corrections can be made on a cell-by-cell basis, the specifications of optical proximity corrected patterns to be made can be determined for each cell or block.
In one embodiment of the present invention, the step b) may include the step of evaluating effectiveness of optical proximity corrections represented by the interlayer corrected pattern data generated. If the effectiveness of the corrections is negated, the method further includes the step of modifying the interlayer corrected pattern data or the circuit patterns corresponding to the corrected pattern data to make the corrections effective and re-evaluating effectiveness of the corrections. And if the effectiveness of the corrections is affirmed, the method further includes the step of registering the interlayer corrected pattern data at a cell library.
A fifth inventive LSI mask data generating method includes the step of a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns. Each said corrected pattern of the first group is defined by circuit patterns placed to cover multiple layers, while each said corrected pattern of the second group is defined by circuit patterns placed within a single layer. The method further includes the steps of: b) setting specifications of interlayer optical proximity corrected patterns to be made for the first group of corrected patterns; c) designing the circuit patterns; and d) evaluating effectiveness of optical proximity corrections if the interlayer corrected patterns, which have been made for the first group of corrected patterns to the specifications of the interlayer corrected patterns, are used. If the effectiveness of the corrections is negated, the method further includes the step of e) modifying ineffective circuit patterns to make the corrections effective and re-evaluating effectiveness of the corrections. And if the effectiveness of the corrections is affirmed, the method further includes the steps of: f) registering the circuit patterns, belonging to the first and second groups of corrected patterns, at a cell library; g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library; h) setting specifications of intralayer optical proximity corrected patterns to be made for the second group of corrected patterns; i) generating interlayer optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the interlayer corrected patterns; and j) generating intralayer optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the intralayer corrected patterns.
According to the fifth inventive LSI mask data generating method, specifications of interlayer corrected patterns are set for the circuit patterns belonging to the first group of corrected patterns, and those circuit patterns are registered at a cell library. Thereafter, when mask data is generated, interlayer and intralayer corrected patterns with a huge data volume are made using the cell library. Accordingly, that huge volume of data can be managed more easily.
A sixth inventive LSI mask data generating method includes the step of a) classifying multiple circuit patterns included in the LSI into first and second groups of corrected patterns. Each said corrected pattern of the first group is defined by circuit patterns placed to cover multiple layers, while each said corrected pattern of the second group is defined by circuit patterns placed within a single layer. The method further includes the steps of: b) setting specifications of interlayer optical proximity corrected patterns to be made for the first group of corrected patterns; c) designing the circuit patterns; and d) evaluating effectiveness of optical proximity corrections if the interlayer corrected patterns, which have been made for the first group of corrected patterns to the specifications of the interlayer corrected patterns, are used. If the effectiveness of the corrections is negated, the method includes the step of e) modifying ineffective circuit patterns or the specifications of the interlayer corrected patterns corresponding to the circuit patterns to make the corrections effective and re-evaluating effectiveness of the corrections. And if the effectiveness of the corrections is affirmed, the method further includes the steps of: f) registering not only the circuit patterns belonging to the first group of corrected patterns and the specifications of the interlayer corrected patterns corresponding to the circuit patterns, but also the circuit patterns belonging to the second group of corrected patterns at a cell library; g) generating chip-level pattern data from the circuit patterns that have been registered at the cell library; h) generating interlayer optical proximity corrected pattern data from the circuit patterns belonging to the first group of corrected patterns according to the specifications of the interlayer corrected patterns; and i) generating intralayer optical proximity corrected pattern data from the circuit patterns belonging to the second group of corrected patterns according to the specifications of the intralayer corrected patterns.
In one embodiment of the fourth through sixth inventive LSI mask data generating methods, if the corrections are effectively applicable to multiple layouts for circuit patterns, the step of evaluating may include the step of selecting one of the layouts that results in a circuit area equal to or smaller than a predetermined value.
In this particular embodiment, the specifications of the interlayer corrected patterns to be made are preferably determined by a placement rule defining a layer including a gate of a transistor and another layer including an active region.
Alternatively, the specifications of the interlayer corrected patterns to be made may also be determined by a placement rule defining a first interconnection layer and another layer including a contact for electrically connecting the first interconnection layer to a second interconnection layer.
As another alternative, the step of evaluating may include the step of determining whether or not an expected actual size falls within a predetermined range by performing a process simulation including at least one of lithography and etching process steps.
In this case, the lithography process step in the process simulation may include determining whether or not the expected actual size falls within the predetermined range even if an exposure dose or focus has changed so much as to exceed a process margin range.
In this case, it may be determined in the process simulation whether or not an expected size of a transistor in a gate longitudinal direction falls within the predetermined range.
Alternatively, it may also be determined in the process simulation whether or not an expected length of a portion of a transistor gate extending from an active layer in a gate width direction falls within the predetermined range.
Second through seventh inventive methods for forming an LSI pattern each include the steps of: producing a mask in accordance with any of the first through sixth LSI mask data generating methods of the present invention; and defining the circuit patterns on a semiconductor substrate using the mask produced.